By Zhiheng Cao, Shouli Yan
Low-Power High-Speed ADCs for Nanometer CMOS Integration is ready the layout and implementation of ADC in nanometer CMOS procedures that in attaining decrease energy intake for a given velocity and determination than past designs, via architectural and circuit options that reap the benefits of special good points of nanometer CMOS procedures. A section lock loop (PLL) clock multiplier has additionally been designed utilizing new circuit concepts and effectively demonstrated.
1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. utilizing offset canceling comparators and capacitor networks applied with small worth interconnect capacitors to interchange resistor ladder/multiplexer in traditional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz enter. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz inner clock in 130nm CMOS. a brand new kind of structure that mixes flash and SAR allows the bottom energy intake, 6-bit >1GS/s ADC suggested up to now. This layout could be a drop-in alternative for current flash ADCs because it does require any post-processing or calibration step and has an identical latency as flash. three) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for producing sampling clock to the SAR ADC. a brand new loop filter out constitution allows part blunders preamplification to decrease PLL in-band noise with out expanding loop clear out capacitor measurement.