By Hendrik van der Ploeg
This booklet analyses diversified A/D-converter architectures with an emphasis at the greatest feasible energy potency. It additionally presents an available evaluate of the state-of-the paintings in calibration options for Nyquist A/D converters. The calibration innovations awarded are appropriate to different analog-to-digital platforms, equivalent to these utilized in built-in receivers. they enable implementation with no introducing a pace or energy penalty.
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Extra info for Calibration Techniques in Nyquist A/D Converters (The Springer International Series in Engineering and Computer Science)
This is caused by the fact that in this calculation the folding ampliﬁer gain Afa is assumed to have a moderate value of only 4. The folding ampliﬁer input transistors are then dominant in the overall capacitance and the number of comparators hardly inﬂuences the intrinsic capacitance. The interpolation factor is therefore of greater importance. But doubling the interpolation factor only reduces the number of input transistor pairs by half, which reduces the input capacitance of of the dominating folding ampliﬁers only by half.
13: The folding and interpolation architecture The sample-and-hold ampliﬁer (SHA) at the input is required for high-frequency input signals because the folding pre-processing acts as an amplitude-dependent frequency multiplier . Since the folding and interpolating A/D architecture makes its decision in one clock cycle, like the ﬂash architecture it is very suitable for high-speed applications. 36 A/D Converter architecture comparison Accuracy The input signal is sampled by the SHA. The noise sampled in and generated by this SHA directly inﬂuences the accuracy of the conversion.
During sampling, in addition to the input signal thermal noise is also sampled onto this capacitance. 12. 2, to achieve an accuracy of N bits. 20) with NEF as the noise excess factor . 20 can be drawn as a function of the number of bits N. 22. 22 is the total intrinsic capacitance of a two-step A/D converter. The intrinsic capacitance originating from the sample and hold capacitance is small with respect to the intrinsic matching capacitance. 18 µm CMOS, with AVT = 5 mV, β = 7 fFµm2 , V Cox pp = 1 V, NEF = 4 and N = 12, the total intrinsic matching capacitance is 35 pF, while Cintr,SHA is 13 pF.